Following their production, integrated circuits are packaged in a housing. Here, integrated circuits are considerably smaller than the associated housing. The connecting pins for connecting the integrated circuit to an external circuit, which pins are located on the housing, are connected via internal wiring lines to contact PADS in order to make electric contact with the electronic circuit.
FIG. 1 shows an arrangement according to the prior art. The connecting pins fitted to the housing are connected via wiring lines to contact PADS on a circuit integrated in the housing. In this case, the connecting pins are conventionally fitted in the manner of a matrix to the underside of the housing. The contact PADS are located on a line of symmetry S, so that in the event of further miniaturization (shrink) of the integrated circuit within the housing, the position of the contact PADS can remain constant. The size of the integrated circuits or the chip size in the case of conventional chips is around 50 mm2. The further the miniaturization of integrated circuits progresses, the greater the line lengths become of the wiring lines to the external connecting pins.
FIGS. 2a, 2b show the arrangement of connecting pins on the underside of circuits integrated in housings, in accordance with the prior art.
In the arrangement according to the prior art, illustrated in FIG. 2a, the address lines ADR for addressing memory cells within the integrated circuit, and the control signal connecting pins (CMD) for applying control signals are arranged centrally, while the connecting pins are fitted above the data lines (Dq) in four groups in a peripheral position on the underside of the housing.
FIG. 2b shows a further arrangement of connecting pins in integrated circuits according to the prior art. In the arrangement illustrated in FIG. 2b, the address connecting pins ADR, the control signal connecting pins CMD and the data connecting pins DQ are likewise arranged in groups on the underside of the housing. In this case, the control signal connecting pins are located in the center of the housing, while the address connecting pins and the data connecting pins are arranged peripherally. In this case, the data connecting pins DQ are conventionally fitted to the side on which there is a data connecting plug on the circuit board.
The disadvantage of the connecting pin arrangements illustrated in FIGS. 2a, 2b is that the wiring lengths of the wiring lines between peripherally arranged connecting pins and the contact PADS within the integrated circuit increase with increasing miniaturization of the circuit integrated in the housing. Since, at the same time, the operating clock frequencies of modern integrated circuits are increasing and, for example, are already some hundreds of MHz in modern DRAM memories, so that data rates of more than 800 megabit per second can occur, the line inductance of wiring lines between the connecting pins and the contact PADS play an increasing role. The greater the line inductance in the wiring lines, the lower the signal integrity of the signal carried over the wiring line. As compared with the signal frequencies of the data signals DQ, the signal frequencies of the address signals ADR and of the control signals CMD are comparatively low.
The arrangements of the connecting pins illustrated in FIGS. 2a, 2b therefore exhibit the disadvantage that it is precisely the data signals, which have a very high signal frequency, that are arranged in a peripheral position, so that because of the relatively great lengths of the wiring lines and the associated high line inductances, they have a low signal integrity and it is therefore possible for data transmission errors to occur.